NTE4013B & NTE4013Bt integrated circuit cmos, dual d ? type flip ? flop description: the NTE4013B and NTE4013Bt dual d ? type flip ? flops are constructed with mos p ? channel and n ? channel enhancement mode devices in a single monolithic structure. each flip ? flop has indepen- dent data (d), direct set (s), direct reset (r), and clock (c) inputs and complementary outputs (q and q ). these devices may be used as shift register elements or as type t flip ? flops for counter and toggle applications. features: supply voltage range: 3v to 15v high noise immunity: 0.45v dd typ diode protection on all inputs capable of driving two low ? power ttl loads of one low ? power schottky ttl load over the rated temperature range available in two package types: NTE4013B (14 ? lead dip) NTE4013Bt (soic ? 14 surface mount) absolute maximum ratings: (v ss = 0v, note 1 unless otherwise specified) dc supply voltage, v dd ? 0.5 to +18v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input or output voltage (dc or transient), v in , v out ? 0.5 to v dd +0.5v . . . . . . . . . . . . . . . . . . . . . . . . . input or output current (dc or transient), per pin, i in , i out 10ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation, p d 500mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . derate above 65 c 7mw/ c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ambient temperature range, t a ? 55 to +125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 to +150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature (during soldering, 8sec), t l +260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 1. ?absolute maximum ratings? are those values beyond which the safety of the device cannot be guaranteed, they are meant to imply that the device should be operated at these limits. the tables of ?recommended operating conditions? and ?electrical characteristics? provide condi- tions for actual device operation. recommended operating conditions: (v ss = 0v unless otherwise specified) dc supply voltage, v dd +3v dc to +15v dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage, v in 0v dc to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ambient temperature range, t a ? 40 to +85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
electrical characteristics: (v ss = 0v, t a = +25 c unless otherwise specified) parameter symbol v dd test conditions min typ max unit output voltage, ?0? level v ol 5 |i o | < 1.0 a ? ? 0.05 v 10 ? ? 0.05 v 15 ? ? 0.05 v output voltage, ?1? level v oh 5 |i o | < 1.0 a 4.95 ? ? v 10 9.95 ? ? v 15 14.95 ? ? v input voltage, ?0? level v il 5 |i o | < 1.0 a v o = 4.5v or 0.5v ? ? 1.5 v 10 v o = 9v or 1v ? ? 3.0 v 15 v o = 13.5v or 1.5v ? ? 4.0 v input voltage, ?1? level v ih 5 |i o | < 1.0 a v o = 0.5v or 4.5v 3.5 ? ? v 10 v o = 1v or 9v 7.0 ? ? v 15 v o = 1.5v or 13.5v 11.0 ? ? v output drive current, source i oh 5 note 2 v oh = 4.6v ? 0.44 ? 0.88 ? ma 10 v oh = 9.5v ? 1.1 ? 2.25 ? ma 15 v oh = 13.5v ? 3.0 ? 8.8 ? ma output drive current, sink i ol 5 note 2 v ol = 0.4v 0.44 0.88 ? ma 10 v ol = 0.5v 1.1 2.25 ? ma 15 v ol = 1.5v 3.0 8.8 ? ma input current i in 15 v in = 0v ? ? 10 ? 5 ? 0.3 a 15 v in = 15v ? 10 ? 5 0.3 a quiescent current (per package) i dd 5 v in = v dd or v ss ? ? 4.0 a 10 ? ? 8.0 a 15 ? ? 16.0 a note 2. i oh and i ol are measured one output at a time. ac electrical characteristics: (c l = 50pf, r l = 200k, t a = +25 c, note 3 unless otherwise specified) parameter symbol v dd test conditions min typ max unit clock operation propagation delay time t phl , t plh 5 ? 200 350 ns 10 ? 80 160 ns 15 ? 65 120 ns transition time t thl , t tlh 5 ? 100 200 ns 10 ? 50 100 ns 15 ? 40 80 ns minimum clock pulse width t wl , t wh 5 ? 100 200 ns 10 ? 40 80 ns 15 ? 32 65 ns maximum clock rise and fall time t rcl , t fcl 5 ? ? 15 s 10 ? ? 10 s 15 ? ? 5 s note 3. ac paramters are guaranteed by dc correlated testing.
ac electrical characteristics (cont?d): (c l = 50pf, r l = 200k, t a = +25 c, note 3 unless otherwise specified) parameter symbol v dd test conditions min typ max unit clock operation (cont?d) minimum setup time t su 5 ? 20 40 ns 10 ? 15 30 ns 15 ? 12 25 ns maximum clock frequency f cl 5 2.5 5.0 ? mhz 10 6.2 12.5 ? mhz 15 7.6 15.5 ? mhz set and reset operation propagation delay time t phl(r) , t plh(s) 5 ? 150 300 ns 10 ? 65 130 ns 15 ? 45 90 ns minimum set and reset pulse width t wh(r) , t wh(s) 5 ? 90 180 ns 10 ? 40 80 ns 15 ? 25 50 ns averag input capacitance c in any ? 5.0 7.5 pf note 3. ac paramters are guaranteed by dc correlated testing. truth table inputs outputs clock data reset set q q 0 0 0 0 1 1 0 0 1 0 x 0 0 q q x x 1 0 0 1 x x 0 1 1 0 x x 1 1 1 1 x = don?t care = level change q1 v dd q2 pin connection diagram v ss q2 1 2 3 4 q1 clock 1 reset 1 5 d1 6 set 1 7 14 13 12 11 clock 2 10 reset 2 9 d2 8 set 2
NTE4013B (14 ? lead dip) NTE4013Bt (soic ? 14) .600 (15.24) 17 14 8 .300 (7.62) .200 (5.08) max .100 (2.45) .099 (2.5) min .785 (19.95) max 061 (1.53) .198 (5.03) .236 (5.99) note: pin1 on beveled edge .154 (3.91) .006 (.152) 7 8 .340 (8.64) 016 (.406) 1 14 .050 (1.27)
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